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? cy62148dv30 4-mbit (512k x 8) mobl ? static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number : 38-05341 rev. *f page 1 of 13 features temperature ranges ? industrial: ?40 c to 85 c very high speed: 55 ns ? wide voltage range: 2.20 v ? 3.60 v pin-compatible with cy62148cv25, cy62148cv30 and cy62148cv33 ultra low active power ? typical active current: 1.5 ma at f = 1 mhz ? typical active current: 8 ma at f = f max (55-ns speed) ultra low standby power easy memory expansion with ce , and oe features automatic power-down when deselected complementary metal oxide semiconductor (cmos) for optimum speed/power available in pb-free 32-pin sm all-outline integrated circuit (soic package) functional description [1] the cy62148dv30 is a high-performance cmos static ram organized as 512k words by 8 bits. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power-down feature that significantly reduces power consumption. the device can be put into standby mode reducing power consumption when deselected ( ce high).the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when: deselected ( ce high) outputs are disabled ( oe high) when the write operation is active( ce low and we low) write to the device by taking chip enable ( ce ) and write enable ( we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). read from the device by taking chip enable ( ce ) and output enable ( oe ) low while forcing write enable ( we ) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. logic block diagram a 1 column decoder row decoder sense amps data in drivers power down we oe i/o 0 i/o 1 i/o 2 i/o 3 512k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 13 ce a 14 a 15 a 16 a 17 a 18 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 note 1. for best practice recommendations, refer to the cypress application note ? system design guidelines ? on http://www.cypress.com. [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 2 of 13 contents pin configuration ............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 electrical characteristics ................................................. 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 data retention characteristics ....................................... 5 data retention waveform ................................................ 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 6 truth table ........................................................................ 8 ordering information ........................................................ 9 ordering code definition ....... ...................................... 9 package diagrams .......................................................... 10 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13 [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 3 of 13 pin configuration 32-pin soic pinout product portfolio product range v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [2] max typ [2] max typ [2] max typ [2] max cy62148dv30ll industrial 2.2 3.0 3.6 55 1.5 3 8 10 2 8 we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 12 13 16 15 29 30 v cc a 3 a 2 a 1 a 17 a 16 oe a 6 a 14 ce i/o 2 i/o 0 i/o 1 a 12 a 7 21 22 19 20 i/o 7 27 28 25 26 17 18 23 24 v ss a 5 a 4 i/o 6 i/o 5 i/o 4 i/o 3 a 10 a 18 a 11 a 0 a 9 a 8 a 13 a 15 top view note 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 4 of 13 maximum ratings (exceeding maximum ratings may impair the useful life of the device. for user guidelines, not tested.) storage temperature... ............... ............... ?65 c to +150 c ambient temperature with ? power applied ............................................. 55 c to +125 c supply voltage to ground ? potential ........................................?0.3 v to v cc(max) + 0.3 v dc voltage applied to outputs ? in high z state [3, 4] ........................ ?0.3 v to v cc(max) + 0.3 v dc input voltage [3, 4] ..................... ?0.3 v to v cc(max) + 0.3 v output current into outputs (low) .............................. 20 ma static discharge voltage........ ........... ............ ............ > 2001v ? (per mil-std-883, method 3015) latch-up current ..................................................... > 200 ma operating range product range ambient temperature v cc [5] cy62148dv30ll industrial ?40 c to +85 c 2.2 v to 3.6 v electrical characteristics over the operating range parameter description test conditions 55 ns unit min typ [2] max v oh output high voltage i oh = ?0.1 ma v cc = 2.20 v 2.0 ? ? v i oh = ?1.0 ma v cc = 2.70 v 2.4 ? ? v v ol output low voltage i ol = 0.1 ma v cc = 2.20 v ? ? 0.4 v i ol = 2.1 ma v cc = 2.70 v ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3v v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3v v v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v cc(max) i out = 0 ma cmos levels 8 10 ma f = 1 mhz ? 1.5 3 ma i sb1 automatic ce ? power-down ? current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ?0.2 v, v in < 0.2 v) f = f max (address and data only), f = 0 ( oe , and we ), v cc =3.60 v ? 2 8 ? a i sb2 automatic ce ? power-down ? current ? cmos inputs ce > v cc ? 0.2 v, ? v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ? 2 8 ? a notes 3. v il(min) = ?2.0 v for pulse durations less than 20 ns. 4. v ih(max) = v cc +0.75 v for pulse durations less than 20 ns. 5. full device ac operation assumes a 100 ? s ramp time from 0 to v cc(min) and 200 ? s wait time after v cc stabilization. [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 5 of 13 capacitance parameter [6] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ) 10 pf c out output capacitance 10 pf thermal resistance parameter [6] description test conditions soic unit ? ja thermal resistance ? (junction to ambient) still air, soldered on a 3 x 4.5 inch, four-layer printed circuit board 55 ? c/w ? jc thermal resistance (junction to case) 22 ? c/w ac test loads and waveforms parameters 2.5 v (2.2 v ? 2.7 v) 3.0 v (2.7 v ? 3.6 v) unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min typ [7] max unit v dr v cc for data retention 1.5 ? ? v i ccdr data retention current v cc = 1.5 v, ce > v cc ?? 0.2 v, v in > v cc ?? 0.2 v or v in < 0.2 v ? 6 ? a t cdr [6] chip deselect to data retention time 0 ? ? ns t r [8] operation recovery time 55 ? ? ns data retention waveform v cc v cc output r2 50 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 fall time: 1 v/ns rise time: 1 v/ns 1.5 v 1.5 v t cdr v dr > 1.5 v data retention mode t r ce v cc notes 6. tested initially and after any design or proce ss changes that may affect these parameters. 7. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c 8. full device ac operation requires linear v cc ramp from v dr to v cc(min) > 100 ? s or stable at v cc(min) ? 100 ? s. [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 6 of 13 switching characteristics (over the operating range) parameter [9] description 55 ns unit min max read cycle t rc read cycle time 55 ? ns t aa address to data valid ? 55 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 55 ns t doe oe low to data valid ? 25 ns t lzoe oe low to low z [10] 5 ? ns t hzoe oe high to high z [10,11] ? 20 ns t lzce ce low to low z [10] 10 ? ns t hzce ce high to high z [10, 11] ? 20 ns t pu ce low to power-up 0 ? ns t pd ce high to power-up ? 55 ns write cycle [12] t wc write cycle time 55 ? ns t sce ce low to write end 40 ? ns t aw address set-up to write end 40 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 40 ? ns t sd data set-up to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [10, 11] ? 20 ns t lzwe we high to low z [10] 10 ? ns switching waveforms figure 1. read cycle no. 1 (address transition controlled) [13, 14] address data out previous data valid data valid t rc t aa t oha notes 9. test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 v/ns), timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? on page 5 . 10. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 11. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 12. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hol d timing should be referenced to the edge of the signal that terminates the write. 13. device is continuously selected. oe , ce = v il . 14. we is high for read cycle. [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 7 of 13 figure 2. read cycle no. 2 ( oe controlled) [15, 16] figure 3. write cycle no. 1 ( we controlled) [17, 18] switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd impedance i cc i sb high data out oe ce v cc supply current address t hd t sd t pwe t sa t ha t aw t wc t hzoe data in valid t sce data i/o address ce we oe note 19 notes 15. we is high for read cycle. 16. address valid prior to or coincident with ce transition low. 17. data i/o is high impedance if oe = v ih . 18. if ce goes high simultaneously with we high, the output remains in high-impedance state. 19. during this period, the i/os are in output state and input signals should not be applied. [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 8 of 13 figure 4. write cycle no. 2 ( ce controlled) [20, 21] figure 5. write cycle no. 3 ( we controlled, oe low) [21] truth table ce we oe inputs/outputs mode power h x x high z deselect/power-down standby (i sb ) l h l data out (i/o 0 -i/o 7 ) read active (i cc ) l h h high z output disabled active (icc) l l x data in (i/o 0 -i/o 7 ) write active (icc) notes 20. data i/o is high impedance if oe = v ih . 21. if ce goes high simultaneously with we high, the output remains in high-impedance state. 22. during this period, the i/os are in output state and input signals should not be applied. switching waveforms (continued) t wc data in valid t aw t sa t pwe t ha t hd t sd t sce ce address we data i/o oe t hd t sd t lzwe t sa t ha t aw t wc t hzwe data in valid t pwe t sce data i/o address ce we note 22 [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 9 of 13 ordering information speed (ns) ordering code package diagram package type operating range 55 CY62148DV30LL-55SXI 51-85081 32-pin soic (pb-free) industrial contact your local cypress sales repres entative for availability of these parts ordering code definition temperature grade: i = industrial package type: sx = 32 pin soic (pb-free) speed grade ll = low power voltage range = 3 v typical d = process technology 130 nm buswidth = 8 density = 4-mbit family code: mobl sram family company id: cy = cypress cy 55 sx 621 4 8 d v30 ll i [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 10 of 13 mobl is a registered trademark, and more battery life is a trademark, of cypress semiconductor. all product and company names m entioned in this document may be the trademarks of their respective holders. package diagrams 51-85081 *c 32-pin (450 mil) molded soic, 51-85081 [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 11 of 13 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor i/o input/output mobl more battery life soic small-outline integrated circuit sram static random access memory symbol unit of measure ns nano seconds v volts a micro amperes ma milli amperes pf pico farad c degree celsius w watts [+] feedback
cy62148dv30 document number : 38-05341 rev. *f page 12 of 13 document history page document title:cy62148dv30, 4-mbit (512k x 8) mobl ? static ram document number: 38-05341 rev. ecn no. issue date orig. of change description of change ** 127480 06/17/03 hrt created new data sheet *a 131041 01/23/04 cbd changed from advance to preliminary *b 222180 see ecn aju changed from preliminary to final added 70 ns speed bin modified footnote #6 and #12 removed max value for v dr on ?data retention characteristics? table modified input and output capacitance values added pb-free ordering information removed 32-pin stsop package *c 498575 see ecn nxr added automotive-a operating range removed soic package from product offering updated ordering information table *d 729917 see ecn vkn added soic package and its related information updated ordering information table *e 2896036 03/19/10 aju removed inactive parts from ordering information. added table of contents. updated packaging information updated links in sales, solutions, and legal information. *f 3166059 02/08/2011 rame removed automotive related info removed 70 ns speed bin related info remove tsop and vfbga package related info updated as per new template added acronyms and units of measure table added ordering code definition details [+] feedback
document number : 38-05341 rev. *f revised february 8, 2011 page 13 of 13 all products and company names mentioned in this document may be the trademarks of their respective holders. cy62148dv30 ? cypress semiconductor corporation, 2010-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/ go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/ image psoc cypress.com/go/psoc touch sensing cypress.com/go/ touch usb controllers cypress.com/go/ usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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